VEGA has to wear ideal for processing huge amounts of data that require quick memory access. Memory cards family Vega allows to address very large sets of data in different types of memory. The controller is in the chipset graphics can access the cache memory within the integrated modules (packages), and for them, a flexible, programmable way, using the methods of accurate data transmission. Among the important news of the new GPU generations from AMD, we find:
- Advanced cooling system – the use of technology HBM2, which allows you to transfer terabytes of data per second (doubling the bandwidth-on – pin in comparison with the previous generation HBM). Module HBM2 offer large capacity, occupying less than half space required by the subsystem GDDR5. The GPU architecture VEGA is optimized for streaming of very large datasets and can work with multiple types of memory, the size of the address book, reaching the 512 TB
- geometric new generation - allows the programmer to use the efficiency of processing complex geometries, and thus provide more than 200 percent increase in throughput per clock tick compared to previous generations of Radeon cards. New solution is also improved mechanism for load control, which manages smart manufacturer, ensuring stable performance.
- compute Engine is a new generation -the basis of the new architecture is a new mechanism that is based on flexible compute units may process 8-, 16-, 32 – and 64-bit operations in each cycle of the timer 2 . These units, as they are so optimized to achieve much higher frequency than previous generations.
- Advanced engine display – a new mechanism of control pixels uses technology DSBR (Draw Stream of the Binning Rasterizer), which was designed to increase performance and energy efficiency. It can also support a pixel in the “fetch time station once” with the integrated intelligent systems first removing invisible pixels, and finally, introducing the scene. The engine display on the graphics cards of the family of VEGA is connected to the cache memory of the second level, which allows considerably reducing the excess load during tasks that are in frequent operations like “read-after-write”.
products using the new architecture to hit the market in the first half of 2017.
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