AMD revealed today the first details about the architecture of graphics processors of the next generation, that is, the family VEGA - this is being developed by from 5 years and provide new opportunities in games and professional applications, and machine learning.
according to the manufacturer, thanks to intensive data processing and parallel nature of the gpu, VEGA ideally suited for handling huge amounts of data requiring quick access to a powerful memory. Thanks to the new podsystemowi memory can and should be, for addressing very large sets of data in different types of memory controller in chipset graphics VEGA can access the cache memory in the framework of integrated modules and outside of them using the methods of accurate data transfer.
AMD among the most important improvements of the maps of the family of VEGA lists:
– advanced cooling system – a new architecture to create a new memory hierarchy for a graphical system that might due to the cache memory and controller technology HBM2, which allows you to transfer terabytes of data per second, which provides a doubling of bandwidth-on-pin in comparison with the previous generation HBM.
– geometric new generation modern games and professional applications use incredibly complex geometry and the new geometry graphics family ensure VEGA has more than a 200 percent increase in throughput per clock tick compared to previous generations of Radeon cards.
– the compute engine of the latest generation – the basis of the new architecture is a new mechanism that on the basis of a flexible compute units may process 8-, 16-, 32 – and 64-bit operations in each cycle of time, these devices are so highly optimized to achieve much higher frequency than previous generations.
– new engine display – a new mechanism of control pixels uses technology DSBR (Draw Stream of the Binning Rasterizer), which was designed to increase performance and energy efficiency. The engine display on the graphics cards of the family of VEGA is connected to the cache memory of the second level, which allows considerably reducing the excess load during tasks that are in frequent operations like “read-after-write”.
Products that use the new architecture to hit the market in the first half of 2017.
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